Contact

Position:
PostDoc Researcher
Address:
Valencia
Email:
This email address is being protected from spambots. You need JavaScript enabled to view it.
Phone:
+34963877007x75745

Image & Curriculum Vitae

Image & Curriculum Vitae :

Publications

  1. R Tornero, J M Ordua, , Jose Flich and Jose Duato. CART: Communication-Aware Routing Technique for Application-Specific NoCs. In Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on. 2008, 26 -31. URL, DOI BibTeX

    @conference{4669215,
    	author = "R. Tornero and J.M. Ordua and , and Flich, Jose and Duato, Jose",
    	abstract = "Networks on Chip (NoCs) have been shown as an efficient solution to the complex on-chip communication problems derived from the increasing number of processor cores. One of the key issues in the design of NoCs is the reduction of both area and power dissipation. As a result, two-dimensional meshes have become the preferred topology, since it offers low and constant link delay. Unfortunately, manufacturing defects or even real-time failures often make the resulting topology to become irregular, preventing the use of traditional routing algorithms. This scenario shows the need for topology-agnostic routing algorithms that provide a valid routing solution when applied over any topology. Moreover, in order to deal with run-time failures, the routing algorithm should be able to fit runtime constraints. This paper proposes a new communication-aware routing technique, referred to as CART, that optimizes the network performance for application-specific NoCs. CART combines a flexible, topology-agnostic routing algorithm with a communication-aware mapping technique that matches the traffic generated by the application with the available network bandwidth. Since the mapping technique can be pruned as needed in order to fit either quality function values or time constraints, CART can be adapted to fit with different computational costs. The evaluation results show that CART significatively improves network performance in terms of both latency and power consumption.",
    	booktitle = "Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on",
    	doi = "10.1109/DSD.2008.19",
    	isbn = "978-0-7695-3277-6",
    	keywords = "CART;application-specific NoC;communication-aware mapping technique;communication-aware routing technique;complex on-chip communication problems;network-on-chip;power dissipation;topology-agnostic routing algorithms;two-dimensional meshes;network routing;",
    	month = "3-5",
    	pages = "26 -31",
    	title = "{CART}: {C}ommunication-{A}ware {R}outing {T}echnique for {A}pplication-{S}pecific {N}o{C}s",
    	url = "http://dx.doi.org/10.1109/DSD.2008.19",
    	year = 2008
    }
    
  2. Jose Flich, Rafael Tornero, Jose Maria Martínez and Carles Hernández. Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. 2018 International Conference on Embed- ded Computer Systems: Architectures, Modeling, and Simulations (SAMOS XVIII), 2018. BibTeX

    @article{10.1145/3229631.3239368,
    	author = "Flich, Jose and Tornero, Rafael and Mart{\'i}nez, Jose Maria and Hern{\'a}ndez, Carles",
    	abstract = {The transition to Exascale computing is going to be characterised by an increased range of application classes. In addition to traditional massively parallel "number crunching" applications, new classes are emerging such as real-time HPC and data-intensive scalable computing. Furthermore, Exascale computing is characterised by a "democratisation" of HPC: to fully exploit the capabilities of Exascale-level facilities, HPC is moving towards enabling access to its resources to a wider range of new players, including SMEs, through cloud-based approaches [1]. Finally, the need for much higher energy efficiency is pushing towards deep heterogeneity, widening the range of options for acceleration, moving from the traditional CPU-only organization, to the CPU plus GPU which currently dominates the Green500¹, to more complex options including programmable accelerators and even (reconfigurable) hardware accelerators [2].},
    	journal = "2018 International Conference on Embed- ded Computer Systems: Architectures, Modeling, and Simulations (SAMOS XVIII)",
    	title = "{R}eliable power and time-constraints-aware predictive management of heterogeneous exascale systems",
    	year = 2018
    }
    
  3. Rafael Tornero, Juan M Orduna, Maurizio Palesi and Jose Duato. A communication-aware topological mapping technique for NoCs. 2008, 910 - 919. URL BibTeX

    @conference{20083911589416,
    	author = "Rafael Tornero and Juan M. Orduna and Maurizio Palesi and Duato, Jose",
    	abstract = "Networks-on-Chip (NoCs) have been proposed as a promising solution to the complex on-chip communication problems derived from the increasing number of processor cores. The design of NoCs involves several key issues, being the topological mapping (the mapping of the Intellectual Properties (IPs) to network nodes) one of them. Several proposals have been focused on topological mapping last years, but they require the experimental validation of each mapping considered. In this paper, we propose a communication-aware topological mapping technique for NoCs. This technique is based on the experimental correlation of the network model with the actual network performance, thus avoiding the need to experimentally evaluate each mapping explored. The evaluation results show that the proposed technique can provide better performance than the currently existing techniques (in terms of both network latency and energy consumption). Additionally, it can be used for both regular and irregular topologies. © 2008 Springer-Verlag Berlin Heidelberg.",
    	address = "Las Palmas de Gran Canaria, Spain",
    	issn = 03029743,
    	journal = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
    	key = "Conformal mapping",
    	keywords = "Biological materials;Chlorine compounds;Communication;Energy policy;Microprocessor chips;Systems engineering;Telecommunication;Topology;",
    	note = "Energy consumption;Evaluation results;Experimental validations;Network latencies;Network modelling;Network nodes;Network performances;Networks-on-chip;On-chip communications;Parallel processing;Processor cores;Topological mapping;",
    	pages = "910 - 919",
    	title = "{A} communication-aware topological mapping technique for {N}o{C}s",
    	url = "http://dx.doi.org/10.1007/978-3-540-85451-7_98",
    	volume = "5168 LNCS",
    	year = 2008
    }