1.- Introduction

gMemNoCsim is a set of tools developed by the Parallel Architectures Group to model Network On Chip systems and analyze their performance. This set of tools consists of:

- gMemNoCsim: a Network On Chip simulator.

- CEF_parser: a parser for configuration files written following CEF specifification format.

- GUI: A front-end for gMemNoCsim and CEFParser.

2.- Description

2.1- gMemNoCsim is a written in C Network On Chip simulator capable of modeling the main components:

- Blocks:

* Nodes. Nodes are modeled as a set of Network Interfaces and traffic patterns that will be injected to the network from this Network Interfaces.

* Network Interfaces. NIs are implemented using a queue system divided in virtual networks and virtual channels, managed by an arbiter, and supporting flow control techniques(stop&go: VCTlite and Wormhole, credits).

* Switches. Switches implementation is based in a 4-stages routing scheme: IB(Input Buffering), RT(Routing), VA_SA (Virtual channel Allocation and Swtich Allocation), X(cross).

- Interconection Network: setting connections between all the blocks, enabling the use of virtual networks and virtual channels and modeling communication channels delay.

- Traffic: In this case two options are available: In one hand gMemNoCsim can generate different synthetic traffic paterns emulating: uniform, bit-reversal, bit-complement or point to point flows. But on the other hand, external trace files containing messages description can be used. gMemNoCsim includes functions to analyze the network performance in both transient and permanent states. The data collected from the different monitored parameters is stored in output files to its later processing and analysis, with the supplied GUI tool or with other tools.

The configuration of the network parameters(topology, properties of blocks, traffic, ...) is done using a configuration file written following CEF specification (http://www.nanoc-project.eu/).

2.2.- CEF_parser: CEF_Parser is a file implemented in C/C++ to read and write CEF format configuration files. This parser can be run on 2 different modes:

- Standalone. This mode is intended for the analysis and validation of configuration files. The parser checks that all parametes set in the file match all restrictios specified by CEF. When the file has completely been analyzed, all settings are displayed on screen along with the error and warning messages, if any.

- Combined. This mode allows reading and writing configuration files. Settings read from file are stored in different structures for reading, modifying and writing. New files can also be written from scratch.

2.3.- GUI is a graphic interface developed in java, for both Simulator and CEF_Parser. The purpose of this GUIĀ  is to simplify simulator usage, making the creation of new configuration files(standard or completely customized topologies), the execution of the simulations and the generation of statitiscal graphics in a few steps possible.

3.- Version History

v1.0B: 2011-12-01 First release of gMemNoCsim. (To register and receive by email this software.)