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Projects in Progress
Processor Architecture
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Publications
- Cuesta Sáez, B., Ros, A., Gomez, M. E., Robles, A. & Duato, J (2011). Increasing the Effectiveness of Directory Caches by Deactivating Coherence for Private Memory Blocks. In 38th International Symposium on Computer Architecture (ISCA), pages 93-103. San Jose (California) : Association for Computing Machinery (ACM). [More]
- Trivino, F., Sanchez, J., Alfaro, F. J. & Flich, J. (2011). Virtualizing network-on-chip resources in chip-multiprocessors. Microprocessors and Microsystems, 35(2), 230 - 45. [More]
- Rayo, D. B., Sahuquillo, J., Mohamed, H. H., Petit, S. & Duato, J (2010). Balancing Task Resource Requirements in Embedded Multithreaded Multicore Processors to Reduce Power Consumption. In Proceedings of the 18th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2010), pages 200 - 4. [More]
- Alonso, M., Coll, S., Martínez, J. M., Santonja, V., Lopez, P. & Duato, J. (2010). Power saving in regular interconnection networks. Parallel Computing, 36(12), 696 - 712. [More]
- Morillo, P., Rueda, S., Orduna, J. M. & Duato, J (2010). Ensuring the performance and scalability of peer-to-peer distributed virtual environments. In Future Generation Computer Systems, pages 905 - 915. P.O. Box 211, Amsterdam, 1000 AE, Netherlands. [More]
- Petit, S., Ubal, R., Sahuquillo, J. & Lopez, P (2009). A power-aware hybrid RAM-CAM renaming mechanism for fast recovery. In Computer Design, 2009. ICCD 2009. IEEE International Conference on, pages 150 -157. [More]
- Petit, S., Ubal, R., Sahuquillo, J., Lopez, P. & Duato, J (2009). An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions. In Nunez, A. & Carballo, P. P. (editors), Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on, pages 635 -642. [More]
- Cuesta Sáez, B., Robles, A. & Duato, J (2008). Switch-based packing technique for improving token coherence scalability. In, pages 80 - 87. Dunedin, Otago, New zealand. [More]
- Pakin, S., Stunkel, C., Flich, J., Alfaro, F., Almasi, G., Bilas, A. et al. (2008). Workshop 9 Introduction: The Workshop on Communication Architecture for Clusters - CAC 2008. IPDPS Miami 2008 - Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM, IEEE Computer Societ. [More]
- Ubal, R., Sahuquillo, J., Petit, S., Hassan, H. & Lopez, P (2007). Leakage Current Reduction in Data Caches on Embedded Systems. In Intelligent Pervasive Computing, 2007. IPC. The 2007 International Conference on, pages 45 -50. [More]
- Ubal, R., Sahuquillo, J., Petit, S. & Lopez, P (2007). Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. In Computer Architecture and High Performance Computing, 2007. SBAC-PAD 2007. 19th International Symposium on, pages 62 -68. [More]
- Ubal, R., Sahuquillo, J., Petit, S., Lopez, P. & Duato, J (2007). VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors. In Parallel Architecture and Compilation Techniques, 2007. PACT 2007. 16th International Conference on, pages 429 -429. [More]
- Alfaro, F. J., Sanchez, J. L. & Duato, J. (2004). QoS in InfiniBand subnetworks. IEEE Transactions on Parallel and Distributed Systems, 15(9), 810 - 23. [More]
- Alonso, M. & Santonja, V (1999). A new destage algorithm for disk cache: DOME. In EUROMICRO Conference, 1999. Proceedings. 25th, pages 416 - 23. IEEE Computer Society Press. [More]
- Santonja, V., Alonso, M., Molero, X., Serrano, J., Gil, P. & Ors, R (1996). Dependability models of RAID using stochastic activity networks. In Hlawiczka, Andrzej, Silva, João, Simoncini & Luca (editors), Dependable Computing — EDCC-2. Springer Berlin / Heidelberg. [More]