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Swicth Architectures
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Publications
- Roca, A., Flich, J., Silla, F. & Duato, J (2010). A Latency-Efficient Router Architecture for CMP Systems. In Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference on, pages 165 -172. [More]
- Coll, S., Mora, F. J., Duato, J. & Petrini, F. (2009). Efficient and scalable hardware-based multicast in fat-tree networks. IEEE Transactions on Parallel and Distributed Systems, 20(9), 1285 - 1298. [More]
- Mora, G., Garcia, P. J., Flich, J. & Duato, J (2007). RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management. In Parallel Processing, 2007. ICPP 2007. International Conference on, pages 74 -74. [More]
- Gilabert, F., Gomez, M. E., Lopez, P. & Duato, J (2006). On the influence of the selection function on the performance of fat-trees. In, pages 864 - 73. Berlin, Germany. [More]
- Nachiondo, T., Flich, J. & Duato, J (2005). Efficient reduction of HOL blocking in multistage networks. In Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International, pages 8 pp.. [More]
- Alonso, M., Martínez, J. M., Santonja, V., Lopez, P. & Duato, J (2005). Power saving in regular interconnection networks built with high-degree switches. In, pages 10 pp. -. Los Alamitos, CA, USA. [More]
- Duato, J., Flich, J. & Nachiondo, T (2004). A cost-effective technique to reduce HOL blocking in single-stage and multistage switch fabrics. In Parallel, Distributed and Network-Based Processing, 2004. Proceedings. 12th Euromicro Conference on, pages 48 - 53. [More]
- Gomez, M. E. & Santonja, V (1999). Self-similarity in I/O workload: analysis and modeling. In, pages 97 - 104. Los Alamitos, CA, USA. [More]
- Duato, J., Lopez, P. & Yalamanchili, S (1997). Deadlock- and livelock-free routing protocols for wave switching. In Parallel Processing Symposium, 1997. Proceedings., 11th International, pages 570 -577. [More]