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Flich, Jose

Personal Information:

Position: Researcher (Associate Professor) Flich, Jose
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Phone or fax: +34963877007x75753
Location: Valencia
Description:

Position

As of January 2010, full-time associate professor at the Universidad Politécnica de Valencia, in the Parallel Arquitectures Group in the School of Engineering in Computer Science

 

Research Topics

   Networks on chip. Routing algorithms and their implementations to address new challenges when building the on-chip network, including fault-tolerance, power management issues, virtualization. New router architectures and topologies for on-chip networks. Interaction of cache coherency protocols and the on-chip network in CMP tile-based systems. Congestion management in on-chip networks. Router designs for efficient on-chip interconnects. On-chip networks for embedded systems (addressing heterogeneity). High performance (off-chip) interconnects. InfiniBand-like networks, addressing routing algorithms, congestion management techniques and fault-tolerant algorithms. Quality of service

Much of this research has been performed as part of national and international research projects, framed in different funded projects like NaNoC, COMCAS, Consolider-Ingenio 2010, CICYT.

The following is a list of current or past advised PhD students:

  • Teresa Nachiondo Farinós, Assistant Professor at UPV
  • José Miguel Montañana Aliaga
  • Andrés Mejía Gómez, currently at Intel Santa Clara
  • Gaspar Mora Porta, currently at Intel Santa Clara
  • Samuel Rodrigo Mocholí
  • Jesús Camacho Villanueva
  • Toni Roca

Other advised students working in research projects:

  • José María Martí­nez
  • José Cano Reyes

Publications

  • Hernández, C., Roca, A., Silla, F., Flich, J. & Duato, J. (2012). On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. IEEE Trans. on CAD of Integrated Circuits and Systems, 31(2), 294-307. [More] 
  • Roca, A., Hernández, C., Flich, J., Silla, F. & Duato, J (2011). A Distributed Switch Architecture for On-Chip Networks. In Parallel Processing (ICPP), 2011 International Conference on, pages 21 -30. [More] 
  • Escudero-Sahuquillo, J., Gran, E. G., Garcia, P. J., Flich, J., Skeie, T., Lysne, O. et al (2011). Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks. In Parallel Processing (ICPP), 2011 International Conference on, pages 662 -672. [More] 
  • Camacho Villanueva, J., Flich, J., Roca, A. & Duato, J (2011). PC-Mesh: A Dynamic Parallel Concentrated Mesh. In Parallel Processing (ICPP), 2011 International Conference on, pages 642 -651. [More] 
  • Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al. (2011). Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 30(4), 534 -547. [More] 
  • Hernández, C., Roca, A., Flich, J., Silla, F. & Duato, J. (2011). Fault-Tolerant Vertical Link Design for Effective 3D Stacking. IEEE Computer Architecture Letters, 99(RapidPosts). [More] 
  • Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al (2011). Cost-efficient on-chip routing implementations for CMP and MPSoC systems. In, pages 534 - 547. 445 Hoes Lane / P.O. Box 1331, Piscataway, NJ 08855-1331, United States. [More] 
  • Hernández, C., Roca, A., Flich, J., Silla, F. & Duato, J. (2011). Characterizing the impact of process variation on 45 nm NoC-based CMPs. Journal of Parallel and Distributed Computing, 71(5), 651 - 663. [More] 
  • Trivino, F., Sanchez, J., Alfaro, F. J. & Flich, J. (2011). Virtualizing network-on-chip resources in chip-multiprocessors. Microprocessors and Microsystems, 35(2), 230 - 45. [More] 
  • Escudero-Sahuquillo, J., Garcia, P. J., Quiles, F. J., Flich, J. & Duato, J. (2011). Cost-effective queue schemes for reducing head-of-line blocking in fat-trees. Concurrency Computation Practice and Experience, 12(15). [More] 
  • Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al. (2011). Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(4), 534 - 47. [More] 
  • Camacho Villanueva, J., Flich, J., Duato, J., Eberle, H. & Olesinski, W (2011). A power-efficient network on-chip topology. In Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip, pages 23-26. New York, NY, USA : ACM. [More] 
  • Camacho Villanueva, J., Flich, J., Duato, J., Eberle, H. & Olesinski, W (2011). Towards an Efficient NoC Topology through Multiple Injection Ports. In Digital System Design (DSD), 2011 14th Euromicro Conference on, pages 165 -172. [More] 
  • Escudero-Sahuquillo, J., Garcia, P. J., Quiles, F. J., Flich, J. & Duato, J (2010). Cost-Effective Congestion Management for Interconnection Networks Using Distributed Deterministic Routing. In 16th International Conference on Parallel and Distributed Systems (ICPADS 2010). Shanghai, China. [More] 
  • Roca, A., Flich, J., Silla, F. & Duato, J (2010). VCTlite: Towards an Efficient Implementation of Virtual Cut-Through Switching in On-Chip Networks. In 17th Int'l Conference on High Performance Computing (HiPC). Goa,India. [More] 
  • Gilabert, F., Silla, F., Gomez, M. E., Lodde, M., Roca, A., Flich, J. et al. (2010). Designing Network On-Chip Architectures in the Nanoscale Era. CRC Press. [More] 
  • Roca, A., Flich, J., Silla, F. & Duato, J (2010). A Latency-Efficient Router Architecture for CMP Systems. In Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference on, pages 165 -172. [More] 
  • Nachiondo, T., Flich, J. & Duato, J. (2010). Buffer Management Strategies to Reduce HoL Blocking. Parallel and Distributed Systems, IEEE Transactions on, 21(6), 739 - 753. [More] 
  • Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al (2010). Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. In Networks-on-Chip (NOCS), 2010 Fourth ACM/IEEE International Symposium on, pages 25 -32. [More] 
  • Hernández, C., Roca, A., Silla, F., Flich, J. & Duato, J (2010). Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. In 2010 ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pages 35 - 42. Grenoble, France : ACM. [More] 
  • Triviño, F., Sánchez, J. L., Alfaro, F. J. & Flich, J. (2010). Virtualizing network-on-chip resources in chip-multiprocessors. Microprocessors and Microsystems, In Press, Uncorrected Proof, -. [More] 
  • Rodrigo, S., Hernández, C., Flich, J., Silla, F., Duato, J., Medardoni, S. et al (2009). Yield-oriented evaluation methodology of network-on-chip routing implementations. In System-on-Chip, 2009. SOC 2009. International Symposium on, pages 100 -105. [More] 
  • Rodrigo, S., Medardoni, S., Flich, J., Bertozzi, D. & Duato, J. (2009). Efficient implementation of distributed routing algorithms for NoCs. Computers Digital Techniques, IET, 3(5), 460 -475. [More] 
  • Chirivella, V., Alcover, R., Flich, J. & Duato, J (2009). Dependability analysis of a fault-tolerant network reconfiguring strategy. In Sips, H., Epema, D. & Lin, H.-X. (editors), Euro-Par 2009 Parallel Processing, pages 1040 - 1051. Delft, Netherlands : Springer. [More] 
  • Mejia, A., Palesi, M., Flich, J., Kumar, S., Lopez, P., Holsmark, R. et al. (2009). Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 17(3), 356 -369. [More] 

Theses

 

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