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Ros, Alberto

Personal Information:

Position: Former Member Ros, Alberto
Phone or fax: +34649163986
Location: Valencia

Publications

  • Valls, J. J., Ros, A., Gomez, M. E. & Sahuquillo, J. (2016). A Directory Cache with Dynamic Private-Shared Partitioning. 2016 IEEE 23rd International Conference on High Performance Computing (HiPC). [More] 
  • Valls, J. J., Ros, A., Gomez, M. E. & Sahuquillo, J. (2016). The Tag Filter Architecture: An energy-efficient cache and directory design. Journal of Parallel and Distributed Computing(100). [More] 
  • Valls, J. J., Sahuquillo, J., Ros, A. & Gomez, M. E. (2015). PS directory: A scalable multilevel directory cache for CMPs. The Journal of Supercomputing, 8(71), 2847-2876. [More] 
  • Valls, J. J., Sahuquillo, J., Ros, A. & Gomez, M. E. (2015). The Tag Filter Cache: An Energy-Efficient Approach. 23rd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP). [More] 
  • Valls, J. J., Ros, A., Gomez, M. E. & Sahuquillo, J. (2015). PS-Cache: an energy-efficient cache design for chip multiprocessors. The Journal of Supercomputing, 1(71), 67-86. [More] 
  • Cuesta Sáez, B., Ros, A., Gomez, M. E., Robles, A. & Duato, J (2011). Increasing the Effectiveness of Directory Caches by Deactivating Coherence for Private Memory Blocks. In 38th International Symposium on Computer Architecture (ISCA), pages 93-103. San Jose (California) : Association for Computing Machinery (ACM). [More] 
  • Ros, A., Acacio, M. E. & Garcia, J. M. (2010). A Direct Coherence Protocol for Many-Core Chip Multiprocessors. Parallel and Distributed Systems, IEEE Transactions on, 21(12), 1779 -1792. [More] 
  • Ros, A., Cuesta Sáez, B., Fernández-Pascual, R., Gomez, M. E., Acacio, M. E., Robles, A. et al (2010). EMC^2: Extending Magny-Cours Coherence for Large-Scale Servers. In 17th Int'l Conference on High Performance Computing (HiPC). Goa, India. [More] 
  • Ros, A., Cintra, M., Acacio, M. E. & Garcia, J. M (2009). Distance-aware round-robin mapping for large NUCA caches. In High Performance Computing (HiPC), 2009 International Conference on, pages 79 -88. [More] 
  • Ros, A., Acacio, M. E. & Garcia, J. M (2008). DiCo-CMP: Efficient cache coherency in tiled CMP architectures. In Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on, pages 1 -11. [More] 

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