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Petit, Salvador

Personal Information:

Position: Researcher (Associate Professor) Petit, Salvador
Email: This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Phone or fax: +34963877007 x 85709
Location: Valencia
Description:

Salvador Petit received his Ph.D. degree in computer engineering from the Universidad Politécnica de Valencia. Currently, he is an Associate Professor in the Computer Engineering Department at the UPV. His research topics include multithreaded and multicore processors, as well as memory hierarchy design and real-time systems. He is a member of the IEEE Computer Society.

Publications

  • Feliu, J., Petit, S., Sahuquillo, J. & Duato, J. (2014). Cache-hierarchy Contention Aware Scheduling in CMPs. IEEE Transactions on Parallel and Distributed Systems, 25(3), 581 - 590. [More] 
  • Feliu, J., Sahuquillo, J., Petit, S. & Duato, J (2014). Addressing bandwidth contention in SMT multicores through scheduling. In International Conference on Supercomputing, ICS'14, pages 167. [More] 
  • Feliu, J., Sahuquillo, J., Petit, S. & Duato, J (2013). Planificación Considerando Degradación de Prestaciones por Contención. In XXIV Jornadas de Paralelismo, JP 2013, Madrid, Sep 17-20, pages 62-67. [More] 
  • Feliu, J., Sahuquillo, J., Petit, S. & Duato, J (2013). L1-Bandwidth Aware Thread Allocation in Multicore SMT Processors. In 22nd International Conference on Parallel Architectures and Compilation Techniques, PACT'13, Edinburgh, United Kingdom, Sep 7-11, pages 123-132. [More] 
  • Feliu, J., Sahuquillo, J., Petit, S. & Duato, J (2013). Using huge pages and performance counters to determine the LLC architecture. In International Conference on Computational Science, ICCS'13, Barcelona, Jun 5-7, pages 2557-2560. [More] 
  • Feliu, J., Sahuquillo, J., Petit, S. & Duato, J (2012). Planificació considerando el ancho de banda de la jerarquía de cache. In XIII Jornadas de Paralelismo, JP 2012, Elche, Sep 19-21, pages 472-477. [More] 
  • Feliu, J., Sahuquillo, J., Petit, S. & Duato, J (2012). Understanding Cache Hierarchy Contention in CMPs to Improve Job Scheduling. In 26th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2012, Shanghai, China, May 21-25, pages 508-519. [More] 
  • Serrano, M., Sahuquillo, J., Petit, S., Hassan, H. & Duato, J. (2011). A cost-effective heuristic to schedule local and remote memory in cluster computers. Journal of Supercomputing, 1 - 19. [More] 
  • Serrano, M., Sahuquillo, J., Mohamed, H. H., Petit, S. & Duato, J (2010). A Scheduling Heuristic to Handle Local and Remote Memory in Cluster Computers. In High Performance Computing and Communications (HPCC), 2010 12th IEEE International Conference on, pages 35 -42. [More] 
  • Rayo, D. B., Sahuquillo, J., Mohamed, H. H., Petit, S. & Duato, J (2010). Balancing Task Resource Requirements in Embedded Multithreaded Multicore Processors to Reduce Power Consumption. In Proceedings of the 18th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2010), pages 200 - 4. [More] 
  • Petit, S., Ubal, R., Sahuquillo, J. & Lopez, P (2009). A power-aware hybrid RAM-CAM renaming mechanism for fast recovery. In Computer Design, 2009. ICCD 2009. IEEE International Conference on, pages 150 -157. [More] 
  • Petit, S., Ubal, R., Sahuquillo, J., Lopez, P. & Duato, J (2009). An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions. In Nunez, A. & Carballo, P. P. (editors), Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on, pages 635 -642. [More] 
  • Ubal, R., Sahuquillo, J., Petit, S., Hassan, H. & Lopez, P (2007). Leakage Current Reduction in Data Caches on Embedded Systems. In Intelligent Pervasive Computing, 2007. IPC. The 2007 International Conference on, pages 45 -50. [More] 
  • Ubal, R., Sahuquillo, J., Petit, S. & Lopez, P (2007). Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. In Computer Architecture and High Performance Computing, 2007. SBAC-PAD 2007. 19th International Symposium on, pages 62 -68. [More] 
  • Ubal, R., Sahuquillo, J., Petit, S., Lopez, P. & Duato, J (2007). VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors. In Parallel Architecture and Compilation Techniques, 2007. PACT 2007. 16th International Conference on, pages 429 -429. [More] 
  • Sahuquillo, J., Tomas, N., Petit, S. & Pont, A. (2007). Spim-Cache: A Pedagogical Tool for Teaching Cache Memories Through Code-Based Exercises. Education, IEEE Transactions on, 50(3), 244 -250. [More] 
  • Ubal, R., Cano Reyes, J., Petit, S. & Sahuquillo, J. (2006). RACFP: a training tool to work with floating-point representation, algorithms, and circuits in undergraduate courses. Education, IEEE Transactions on, 49(3), 321 -331. [More] 
  • Petit, S., Sahuquillo, J. & Pont, A (2005). A comparison study of the HLRC-DU protocol versus a HLRC hardware assisted protocol. In Parallel, Distributed and Network-Based Processing, 2005. PDP 2005. 13th Euromicro Conference on, pages 197 - 204. [More] 
  • Petit, S., Sahuquillo, J., Pont, A. & Kaeli, D (2004). Characterizing the dynamic behavior of workload execution in SVM systems. In Computer Architecture and High Performance Computing, 2004. SBAC-PAD 2004. 16th Symposium on, pages 230 - 237. [More] 
  • Petit, S., Sahuquillo, J. & Pont, A (2002). Characterizing parallel workloads to reduce multiple writer overhead in shared virtual memory systems. In Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on, pages 261 -268. [More] 
  • Petit, S., Sahuquillo, J. & Pont, A (2001). About the sensitivity of the HLRC-DU protocol on diff and page sizes. In Performance Analysis of Systems and Software, 2001. ISPASS. 2001 IEEE International Symposium on, pages 45 -48. IEEE Computer Society Press. [More] 
 

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