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Camacho Villanueva, Jesus

Personal Information:

Position: Former Member
Phone or fax: +963877007x75745
Location: Valencia

Publications

  • Camacho Villanueva, J., Flich, J., Roca, A. & Duato, J (2011). PC-Mesh: A Dynamic Parallel Concentrated Mesh. In Parallel Processing (ICPP), 2011 International Conference on, pages 642 -651. [More] 
  • Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al. (2011). Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 30(4), 534 -547. [More] 
  • Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al (2011). Cost-efficient on-chip routing implementations for CMP and MPSoC systems. In, pages 534 - 547. 445 Hoes Lane / P.O. Box 1331, Piscataway, NJ 08855-1331, United States. [More] 
  • Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al. (2011). Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(4), 534 - 47. [More] 
  • Camacho Villanueva, J., Flich, J., Duato, J., Eberle, H. & Olesinski, W (2011). A power-efficient network on-chip topology. In Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip, pages 23-26. New York, NY, USA : ACM. [More] 
  • Camacho Villanueva, J., Flich, J., Duato, J., Eberle, H. & Olesinski, W (2011). Towards an Efficient NoC Topology through Multiple Injection Ports. In Digital System Design (DSD), 2011 14th Euromicro Conference on, pages 165 -172. [More] 
  • Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al (2010). Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. In Networks-on-Chip (NOCS), 2010 Fourth ACM/IEEE International Symposium on, pages 25 -32. [More] 
  • Camacho Villanueva, J., Flich, J., Duato, J., Eberle, H., Gura, N. & Olesinski, W (2009). A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors. In Network on Chip Architectures, 2009. NoCArc 2009. 2nd International Workshop on, pages 51 -56. [More] 
 

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