Position

As of January 2010, full-time associate professor at the Universidad Politécnica de Valencia, in the Parallel Arquitectures Group in the School of Engineering in Computer Science

Research Topics

   Networks on chip. Routing algorithms and their implementations to address new challenges when building the on-chip network, including fault-tolerance, power management issues, virtualization. New router architectures and topologies for on-chip networks. Interaction of cache coherency protocols and the on-chip network in CMP tile-based systems. Congestion management in on-chip networks. Router designs for efficient on-chip interconnects. On-chip networks for embedded systems (addressing heterogeneity). High performance (off-chip) interconnects. InfiniBand-like networks, addressing routing algorithms, congestion management techniques and fault-tolerant algorithms. Quality of service

Much of this research has been performed as part of national and international research projects, framed in different funded projects like NaNoC, COMCAS, Consolider-Ingenio 2010, CICYT.

The following is a list of current or past advised PhD students:

• Teresa Nachiondo Farinós, Assistant Professor at UPV
• José Miguel Montañana Aliaga
• Andrés Mejía Gómez, currently at Intel Santa Clara
• Gaspar Mora Porta, currently at Intel Santa Clara
• Samuel Rodrigo Mocholí
• Jesús Camacho Villanueva
• Toni Roca

Other advised students working in research projects:

• José María Martí­nez
• José Cano Reyes

• Hernández, C., Roca, A., Silla, F., Flich, J. & Duato, J. (2012). On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. IEEE Trans. on CAD of Integrated Circuits and Systems, 31(2), 294-307. [More] 
• Roca, A., Hernández, C., Flich, J., Silla, F. & Duato, J (2011). A Distributed Switch Architecture for On-Chip Networks. In Parallel Processing (ICPP), 2011 International Conference on, pages 21 -30. [More] 
• Escudero-Sahuquillo, J., Gran, E. G., Garcia, P. J., Flich, J., Skeie, T., Lysne, O. et al (2011). Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks. In Parallel Processing (ICPP), 2011 International Conference on, pages 662 -672. [More] 
• Camacho Villanueva, J., Flich, J., Roca, A. & Duato, J (2011). PC-Mesh: A Dynamic Parallel Concentrated Mesh. In Parallel Processing (ICPP), 2011 International Conference on, pages 642 -651. [More] 
• Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al. (2011). Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 30(4), 534 -547. [More] 

• VIRTICAL : SW/HW extensions for virtualized heterogeneous multicore platforms
• Nanoscale Silicon-Aware Network-on-Chip Design Platform
• Server architectures, applications and services
• Extended HyperTransport technology network to improve scalability of web servers.
• Comunication-centric heterogeneous Multi-Core ArchitectureS

• Cost Effective Routing Implementations for On-chip Networks
• Efficient mechanisms to provide fault tolerance in interconnection networks for PC Clusters
• High-performance architectures for high-radix switches.
• Design and Implementation of Efficient Topology Agnostic Routing Algorithms for Interconnection Networks