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Reaño, C., Peña, A. J., Silla, F., Mayo, R., Quintana-Ortí, E. S. & Duato, J (2012). CU2rCU: towards the Complete rCUDA Remote GPU Virtualization and Sharing Solution. In 19th Annual International Conference on High Performance Computing (HiPC). [More]
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Reaño, C., Silla, F. & Vidal, G. (2012). CU2rCU: A CUDA-to-rCUDA Converter. Master Thesis, Universitat Politècnica de València, Spain. [More]
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Hernández, C., Roca, A., Silla, F., Flich, J. & Duato, J. (2012). On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. IEEE Trans. on CAD of Integrated Circuits and Systems, 31(2), 294-307. [More]
- Strano, A., Hernández, C., Silla, F. & Bertozzi, D. (2011). Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design. International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 2(4), 20. [More]
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Hernández, C., Silla, F. & Duato, J (2011). Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations. In Parallel Processing (ICPP), 2011 International Conference on, pages 41 -50. [More]
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Roca, A., Hernández, C., Flich, J., Silla, F. & Duato, J (2011). A Distributed Switch Architecture for On-Chip Networks. In Parallel Processing (ICPP), 2011 International Conference on, pages 21 -30. [More]
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Duato, J., Peña, A. J., Silla, F., Mayo, R. & Quintana-Orti, E. S (2011). Performance of CUDA Virtualized Remote GPUs in High Performance Clusters. In Parallel Processing (ICPP), 2011 International Conference on, pages 365 -374. [More]
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Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al. (2011). Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 30(4), 534 -547. [More]
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Duato, J., Peña, A. J., Silla, F., Mayo, R. & Quintana-Ort, E. S. (2011). Enabling CUDA acceleration within virtual machines using rCUDA. Proceedings of HiPC 2011. [More]
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Hernández, C., Roca, A., Flich, J., Silla, F. & Duato, J. (2011). Fault-Tolerant Vertical Link Design for Effective 3D Stacking. IEEE Computer Architecture Letters, 99(RapidPosts). [More]
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Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al (2011). Cost-efficient on-chip routing implementations for CMP and MPSoC systems. In, pages 534 - 547. 445 Hoes Lane / P.O. Box 1331, Piscataway, NJ 08855-1331, United States. [More]
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Hernández, C., Roca, A., Flich, J., Silla, F. & Duato, J. (2011). Characterizing the impact of process variation on 45 nm NoC-based CMPs. Journal of Parallel and Distributed Computing, 71(5), 651 - 663. [More]
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Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al. (2011). Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(4), 534 - 47. [More]
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Hernández, C., Silla, F. & Duato, J (2011). Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations. In ICPP, pages 41-50. [More]
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Montaner, H., Silla, F., Froning, H. & Duato, J. (2011). A new degree of freedom for memory allocation in clusters. Cluster Computing, 1 - 23. [More]
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Roca, A., Flich, J., Silla, F. & Duato, J (2010). VCTlite: Towards an Efficient Implementation of Virtual Cut-Through Switching in On-Chip Networks. In 17th Int'l Conference on High Performance Computing (HiPC). Goa,India. [More]
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Gilabert, F., Silla, F., Gomez, M. E., Lodde, M., Roca, A., Flich, J. et al. (2010). Designing Network On-Chip Architectures in the Nanoscale Era. CRC Press. [More]
- Strano, A., Hernández, C., Silla, F. & Bertozzi, D (2010). Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip. In System on Chip (SoC), 2010 International Symposium on, pages 43 -48. [More]
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Roca, A., Flich, J., Silla, F. & Duato, J (2010). A Latency-Efficient Router Architecture for CMP Systems. In Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference on, pages 165 -172. [More]
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Montaner, H., Silla, F., Fröning, H. & Duato, J (2010). Getting Rid of Coherency Overhead for Memory-Hungry Applications. In Cluster Computing (CLUSTER), 2010 IEEE International Conference on, pages 48 -57. [More]
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Montaner, H., Silla, F. & Duato, J (2010). A practical way to extend shared memory support beyond a motherboard at low cost. In Proceedings of the 19th ACM International Symposium on High Performance Distributed Computing, pages 155-166. Chicago, Illinois : ACM. [More]
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Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al (2010). Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. In Networks-on-Chip (NOCS), 2010 Fourth ACM/IEEE International Symposium on, pages 25 -32. [More]
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Hernández, C., Roca, A., Silla, F., Flich, J. & Duato, J (2010). Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. In 2010 ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pages 35 - 42. Grenoble, France : ACM. [More]
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Hernández, C., Silla, F. & Duato, J (2010). A Methodology for the Characterization of Process Variation in NoC Links. In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pages 685-690. Dresden, Germany : EDDA. [More]
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Duato, J., Peña, A. J., Silla, F., Mayo, R. & Quintana-Ort, E. S (2010). rCUDA: Reducing the number of GPU-based accelerators in high performance clusters. In High Performance Computing and Simulation (HPCS), 2010 International Conference on, pages 224 - 231. Caen, France. [More]
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