C. Hernández received the MS in Telecomunications Engineering and Computer Engineering from the Technical University of Valencia, Spain, in 2006 and 2008, respectively. Currently, he is a Ph.D. candidate at the Technical University of Valencia. His research areas include, but are not limited to: CMOS process variation modeling, Network-on-chip switch architectures, and NoC energy and perfomance modeling.

• Hernández, C., Roca, A., Silla, F., Flich, J. & Duato, J. (2012). On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. IEEE Trans. on CAD of Integrated Circuits and Systems, 31(2), 294-307. [More] 
• Strano, A., Hernández, C., Silla, F. & Bertozzi, D. (2011). Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design. International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 2(4), 20. [More] 
• Hernández, C., Silla, F. & Duato, J (2011). Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations. In Parallel Processing (ICPP), 2011 International Conference on, pages 41 -50. [More] 
• Roca, A., Hernández, C., Flich, J., Silla, F. & Duato, J (2011). A Distributed Switch Architecture for On-Chip Networks. In Parallel Processing (ICPP), 2011 International Conference on, pages 21 -30. [More] 
• Hernández, C., Roca, A., Flich, J., Silla, F. & Duato, J. (2011). Fault-Tolerant Vertical Link Design for Effective 3D Stacking. IEEE Computer Architecture Letters, 99(RapidPosts). [More] 
• Hernández, C., Roca, A., Flich, J., Silla, F. & Duato, J. (2011). Characterizing the impact of process variation on 45 nm NoC-based CMPs. Journal of Parallel and Distributed Computing, 71(5), 651 - 663. [More] 
• Hernández, C., Silla, F. & Duato, J (2011). Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations. In ICPP, pages 41-50. [More] 
• Gilabert, F., Silla, F., Gomez, M. E., Lodde, M., Roca, A., Flich, J. et al. (2010). Designing Network On-Chip Architectures in the Nanoscale Era. CRC Press. [More] 
• Strano, A., Hernández, C., Silla, F. & Bertozzi, D (2010). Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip. In System on Chip (SoC), 2010 International Symposium on, pages 43 -48. [More] 
• Hernández, C., Roca, A., Silla, F., Flich, J. & Duato, J (2010). Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. In 2010 ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pages 35 - 42. Grenoble, France : ACM. [More] 
• Hernández, C., Silla, F. & Duato, J (2010). A Methodology for the Characterization of Process Variation in NoC Links. In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pages 685-690. Dresden, Germany : EDDA. [More] 
• Rodrigo, S., Hernández, C., Flich, J., Silla, F., Duato, J., Medardoni, S. et al (2009). Yield-oriented evaluation methodology of network-on-chip routing implementations. In System-on-Chip, 2009. SOC 2009. International Symposium on, pages 100 -105. [More] 
• Hernández, C., Silla, F., Santonja, V. & Duato, J (2009). A new mechanism to deal with process variability in NoC links. In IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium, pages IEEE Computer Societ. Rome, Italy. [More] 

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