This project aims to develop several techniques to improve the performance and reliability of current architectures for Centres servers Data and Internet servers, for a given cost and power consumption. In this project do research on issues of processor architectures, memory and networks interconnection, multiprocessor systems, system software, parallel file systems,
dynamic load balancing techniques to efficiently support data acquisition and client access via wireless networks and to improve the quality of access to resources through the Grid. This research project combines incremental research breaker and the implementation of a prototype. Among the cutting-edge research activities, develop techniques to execute instructions out of order without checkpointing will reduce dramatically negative impact of increasing memory latency, an organization of cache memory without reducing the average time to access memory, a network architecture interconnection with a latency of message an order of magnitude lower than at present, and study automatic extraction techniques of parallel non-speculative thread-level hardware (threads). This project is also developing new results in the research followed traditionally by our group, including research on processor microarchitecture, reduce processor power consumption, chip multiprocessors, protocols cache coherence, switch architecture, congestion control, routing, network fault tolerant, reducing the energy consumption of network, support for QoS (Both within the interconnection network as access to the server via the Grid) reconfiguration of the network, techniques to efficiently support wireless access to servers, parallel file systems, system software for parallel computers, techniques and load balancing. Finally, some of these techniques will be implemented, adjusted, and tested in a test bed to demonstrate the feasibility of the proposals.