Projects in Progress
Projects
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High-performance, Reliable Architectures for Data Centers and Internet Servers
Research Area: High Performance ClustersProject leaders
Duato, JoseFunding
,EUR 1.643.255,-
This project aims to develop several techniques to improve the performance and reliability of current architectures for Centres servers Data and Internet servers, for a given cost and power consumption. In this project do research on issues of processor architectures, memory and networks interconnection, multiprocessor systems, system software, parallel file systems,
dynamic load balancing techniques to efficiently support data acquisition and client access via wireless networks and to improve the quality of access to resources through the Grid. This research project combines incremental research breaker and the implementation of a prototype. Among the cutting-edge research activities, develop techniques to execute instructions out of order without checkpointing will reduce dramatically negative impact of increasing memory latency, an organization of cache memory without reducing the average time to access memory, a network architecture interconnection with a latency of message an order of magnitude lower than at present, and study automatic extraction techniques of parallel non-speculative thread-level hardware (threads). This project is also developing new results in the research followed traditionally by our group, including research on processor microarchitecture, reduce processor power consumption, chip multiprocessors, protocols cache coherence, switch architecture, congestion control, routing, network fault tolerant, reducing the energy consumption of network, support for QoS (Both within the interconnection network as access to the server via the Grid) reconfiguration of the network, techniques to efficiently support wireless access to servers, parallel file systems, system software for parallel computers, techniques and load balancing. Finally, some of these techniques will be implemented, adjusted, and tested in a test bed to demonstrate the feasibility of the proposals.
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Comunication-centric heterogeneous Multi-Core ArchitectureS
Research Area: Network-On-ChipProject leaders
Flich, JoseFunding
,EUR 59.151,-
Este proyecto ha sido financiado por el Ministerio de Industria, Turismo y Comercio, dentro del Plan Nacional de Investigación Cientifica, Desarrollo e Innovación Tecnológica 2008-2011 bajo la subvención TSI-020400-2009-64
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Extended HyperTransport technology network to improve scalability of web servers.
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Server architectures, applications and services
Research Area: High Performance ClustersProject leaders
Duato, JoseFunding
,EUR 855.228,-
Internet and cell phone services, as well as enterprise databases and datacenters, and scientific databases, are usually implemented on high-performance servers (based on cluster architectures). This project aims at developing several techniques to improve the performance and reliability of current high-performance servers, as well as reducing their cost and power consumption. In addition to these architectural enhancements, we will improve the services offered by those servers, developing the corresponding applications, as well as the access to them, especially when clients are connected through wireless networks.To achieve this goal, this project will deliver new results along the research lines traditionally followed by our group, including research on processor, memory, and interconnect architectures, multiprocessor systems, system software, client access through wireless networks, and several applications and services offered by the servers. The project will also start research on new topics in this context, including networks on chip, accelerators based on graphics cards, sensor networks, video transcoding, and sensor network assisted robot tracking. More precisely, we will develop research on chip multiprocessor architecture and networks on chip, aiming at increasing performance, reducing power consumption, increasing reliability by means of fault tolerant techniques, managing variability, increasing flexibility by means of virtualization techniques, and reducing silicon area. Additionally, we will improve the performance and reliability of cache coherence protocols, also codesigning the protocol and the network on chip. We will also develop techniques for transactional memory. We will develop new network topologies that reduce the number of hops and increase the number of alternative paths, also improving routing, congestion management, and quality of service, thus increasing performance and reliability, and reducing power consumption. We will also research on system software for servers, such as parallel file systems, or middleware, such as grid and cloud computing, and on numerical libraries for scientific applications, accelerated by means of graphics cards.On a related area, we will research on techniques to efficiently support wireless access to servers, enhancing the medium access protocols, as well as techniques to reduce bandwidth consumption, such as video transcoding. We will also research on sensor networks, considered as an information sampling subsystem connected to a server, developing medium access control and power reduction techniques.Finally, we also plan to develop parallel applications and services for servers, such as algorithms for artificial perception, Distributed Virtual Environments (DVE), multiagent algorithmsfor crowd simulation, detection of fire frontline by means of sensor networks, and sensor networkassisted robot tracking.
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Nanoscale Silicon-Aware Network-on-Chip Design Platform
Research Area: Network-On-ChipProject leaders
Flich, JoseFunding
,EUR 513.763,-
Project Objectives
The NaNoC project aims at developing an innovative design platform for future Network-on-Chip (NoC) based multi-core systems. This NaNoC design platform intends to master the design complexity of advanced microelectronic systems by enabling strict component oriented architectural design. A compositional approach to NoC design in future multi-core chips is out of the reach of current design methods and tools due to new design constraints.
Requirements for co-design with high-level platform management frameworks facilitates a need for enhanced dynamism and flexibility in NoC composition (e.g., virtualization, power management, thermal management, application management). On the other hand, a higher degree of uncertainty originating from nanoscale IC fabrication technologies raises the need to build reliable systems out of unreliable components. The NaNoC design platform provides design methods and prototype tools to cope with both challenges and to make NoCs a mainstream interconnect backbone for effective system integration. The platform enables NoC component assembly at each layer of the design hierarchy. Therefore, design for manufacturability techniques and tools are developed to preserve yield in the presence of manufacturing defects and circuit performance/power variability.
Above all, the NaNoC design platform fosters the tight cooperation between system research, circuit design and process development by means of a silicon-aware decision making at each layer of the design hierarchy. In this direction, NaNoC not only provides a cross-layer approach to tackle composability challenges (e.g., physical design techniques for enhanced reliability combined with architecture-level techniques for fault containment), but also defines an exchange format for interoperability between design tools for cross-layer optimization. Interoperability between developed NoC design methods/prototype tools and mainstream design toolflows will also be pursued.
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VIRTICAL : SW/HW extensions for virtualized heterogeneous multicore platforms
Research Area: Processor ArchitectureProject leaders
Gomez, Maria E.Funding
,EUR 4.270.000,-
Embedded devices are pervasive in our everyday live and their complexity increases exponentially. Among them, heterogeneous multi-core processors and specific hardware accelerators allow the required computing power while exhibiting a good performance/watt ratio. The flexibility required by them is promoting an application-centric model, which makes future systems face new challenges: Openness (total decoupling from hardware to application software), security, programmability and performance. Virtualization, widely used in the general-purpose computing domain, allows an effective and clean way to isolate applications from hardware, so being suitable to cope with the challenges faced by heterogeneous multi-core embedded systems. However, virtualization on embedded systems is still in its infancy. Their real-time requirements, resource constraints and heterogeneous nature demand for an integral and different approach of the virtualization concept.
The vIrtical project aims the vertical and full development of the virtualization concept addressing the specific requirements for effective embedded virtualization. A virtualization-ready SoC platform and the associated programming models will be developed, tackling all the system layers: applications, programming model, hypervisor and hardware.
This unique integrated approach is able to address the evolution towards heterogeneous multi-cores and even many-cores in embedded systems by focusing not only on the well-known processor virtualization but on the hardware assisted virtualization for the overall SoC. Security and protection, real-time QoS guarantees, reliability, process variation, power savings, and memory coherency will be addressed and will influence the way the system is virtualized. The vIrtical consortium is formed by key European players in the embedded market (UNIBO, UPV, TEI, ST, THALES, ARM, SYSGO, VOSYS), so guaranteeing the right development of the different layers tackled in the virtualization-ready SoC platform...