Improving the Performance of GALS-Based NoCs in the Presence of Process Variation
|Type of Publication:||In Proceedings||Keywords:||integrated circuit design;large scale integration;network-on-chip;performance evaluation;|
|Book title:||2010 ACM/IEEE International Symposium on Networks-on-Chip (NOCS)|
|Pages:||35 - 42|
GALS-based NoCs;chip multiprocessors;network-on-chip;manufacturing deviations;process variation;performance domains;integration scales;
Current integration scales allow designing chip multiprocessors (CMP) where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales cause some unpredictability in manufactured devices because of process variation. In NoCs,variability may affect links and routers causing that they do not match the parameters established at design time. In this paper we first analyze the way that manufacturing deviations affect the components of a NoC by applying a comprehensive and detailed variability model to 200 instances of an 8×8 mesh NoC synthesized using 45 nm technology. A second contribution of this paper is showing that GALS-based NoCs present communication bottlenecks under process variation. To overcome this performance reduction we draft a novel approach, called performance domains, intended to reduce the negative impact of variability on application execution time. This mechanism is suitable when several applications are simultaneously running in the CMP chip.