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A Methodology for the Characterization of Process Variation in NoC Links

Research Area: Network-On-Chip Year: 2010
Type of Publication: In Proceedings Keywords: multiprocessor interconnection networks;network-on-chip;
Authors:
Book title: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
Pages: 685-690
Address: Dresden, Germany
Month: March
ISBN: 978-3-9810801-6-2
Note:
process variation;NoC Links;network-on-chip;chip multiprocessor;process variability;
Abstract:
Associated with the ever growing integration scales is the increase in process variability. In the context of network-on-chip, this variability affects the maximum frequency that could be sustained by each link that interconnects two cores in a chip multiprocessor. In this paper we present a methodology to model delay variations in NoC links. We also show its application to several technologies, namely 45nm, 32nm, 22nm, and 16nm. Simulation results show that conclusions about variability greatly depend on the implementation context.
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