A power-aware hybrid RAM-CAM renaming mechanism for fast recovery
|Research Area:||Processor Architecture||Year:||2009|
|Type of Publication:||In Proceedings||Keywords:||direct-mapped RAM;misprediction recovery penalty;physical registers;pipeline width;power-aware hybrid RAM-CAM renaming mechanism;processor cycle;register renaming;superscalar processors;microprocessor chips;power aware computing;random-access storage;|
|Book title:||Computer Design, 2009. ICCD 2009. IEEE International Conference on|
Modern superscalar processors implement register renaming by using either RAM or CAM tables. The design of these structures should address their access time and misprediction recovery penalty. While direct-mapped RAMs provide faster access times, CAMs are more appropriate to avoid recovery penalties. Although they are more complex and slower, CAMs usually match the processor cycle in current designs. However, they do not scale with the number of physical registers and the pipeline width. In this paper we present a new hybrid RAM-CAM register renaming scheme, which combines the best of both approaches. In a steady state, a RAM provides the current mappings quickly; on mispeculation, a low-complexity CAM enables immediate recovery and further register renaming. Compared to an ideal CAM in a 4-way state-of-the-art superscalar microprocessor, and for almost the same performance (1% slowdown) and area (95% of the ideal CAM size), the proposed scheme consumes about 90% less dynamic energy.