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An Efficient Switching Technique for NoCs with Reduced Buffer Requirements

Research Area: Network-On-Chip Year: 2008
Type of Publication: In Proceedings Keywords: buffer control logic;critical path delay;network clock frequency;network cycle;networks on chip;packet dropping;reduced buffer requirements;switching technique;network-on-chip;performance evaluation;
Authors:
Book title: Parallel and Distributed Systems, 2008. ICPADS '08. 14th IEEE International Conference on
Pages: 713 -720
Month: dec.
ISSN: 1521-9097
Abstract:
Networks on chip (NoCs) communicate the components located inside a chip. Overall system performance depends on NoC performance, that is affected by several factors. One of them is the network clock frequency, imposed by the critical path delay. Recent works show that switch critical path includes buffer control logic. Consequently, by removing switch buffers, switch frequency can be doubled. In this paper, we exploit this idea, proposing a new switching technique for NoCs which requires a reduced amount of storage at the switches. It is based on replacing switch port buffers by single latches. By doing so, network cycle can be reduced, which reduces packet latency. On the other hand, power and area consumption requirements can be reduced. However, since there are no buffers at the switch ports, packets can not be stopped. Stopped packets due to contention are dropped and reinjected from their senders via negative acknowledgments. Packet dropping is strongly reduced by exploiting NoCs wiring capability.
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