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Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip
| Research Area: | Network-On-Chip | Year: | 2010 |
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| Type of Publication: | In Proceedings | Keywords: | GALS networks-on-chip;layout mismatch tolerant design;link delay variations;process variation;self-calibration mechanism;signal misalignments;source synchronous links;synchronization interfaces;transmitter clock;delays;integrated circuit layout;network-on |
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| Book title: | System on Chip (SoC), 2010 International Symposium on | ||
| Pages: | 43 -48 | ||
| Month: | sept. | ||
| ISBN: | 978-1-4244-8279-5 | ||
| Abstract: |
Synchronization interfaces in a network-on-chip (NoC) are becoming vulnerable points that need to be safeguarded against link delay variations and signal misalignments. This paper addresses the challenge of designing a process variation and layout mismatch tolerant link for GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. Then, a suitable delayed replica of the transmitter clock is selected for safe sampling of misaligned data. The paper proves correct operation of the GALS link augmented with the variation detector and compares its reliability with that of a detector-less link, beyond proving robustness with respect to the delay variability affecting the detector itself.
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