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How to reduce packet dropping in a bufferless NoC

Research Area: Network-On-Chip Year: 2011
Type of Publication: Article Keywords: buffer circuits;circuit switching;network-on-chip;
Authors:
Journal: Concurrency and Computation: Practice and Experience Volume: 23
Number: 1 Pages: 86 - 99
ISSN: 1532-0626
Note:
packet dropping reduction;bufferless NoC;networks on-chip;critical path delay;switch clock frequency;blind packet switching;switch port buffers;network traffic range;
Abstract:
Networks on-chip (NoCs) interconnect the components located inside a chip. In multicore chips, NoCs have a strong impact on the overall system performance. NoC bandwidth is limited by the critical path delay. Recent works show that the critical path delay is heavily affected by switch port buffer size. Therefore, by removing buffers, switch clock frequency can be increased. Recently, a new switching technique for NoCs called Blind Packet Switching (BPS) has been proposed, which is based on removing the switch port buffers. Since buffers consume a high percentage of switch power and area, BPS not only improves performance but also reduces power and area. In BPS, as there are no buffers at the switch ports, packets cannot be stopped and stored on them. If contention arises packets are dropped and later reinjected, negatively affecting performance. In order to prevent packet dropping, some techniques based on resource replication have been proposed. In this paper, we propose some alternative and complementary techniques that do not rely on resource replication. By using them, packet dropping is highly reduced. In particular, packet dropping is completely removed for a very wide network traffic range. Moreover, network throughput is increased and packet latency is reduced. © 2010 John Wiley & Sons, Ltd.
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