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Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations

Research Area: Network-On-Chip Year: 2011
Type of Publication: In Proceedings
Authors:
Book title: Parallel Processing (ICPP), 2011 International Conference on
Pages: 41 -50
Month: sept.
ISSN: 0190-3918
Abstract:
Within-die process variation causes cores, memories, and network resources in NoC-based CMPs to present different speeds and leakage power. In this context, thread mapping strategies that consider the effects of process variability on chip resources arise as a suitable choice to maximize performance while energy consumption constraints are satisfied. However, other factors, as the location of memory controllers and the concurrent execution of several applications in the chip, can bound the possible benefits of such mapping strategies. In this paper we propose a mapping strategy, named as uniform regions, that takes variability effects into account when assigning application threads to cores in the chip. More specifically, uniform regions, in terms of operating frequency, that additionally present the highest available frequency, are selected so that the benefits of such a variation-aware mapping strategy in a NoC-based CMP are maximized. We additionally present two different ways of configuring the frequency and voltage of the cores in the selected region. The first one is intended to provide the maximum performance while keeping energy as low as possible, while the second one is much more for energy-aware. The first one reduces the execution time up to a 23 #x025; while reducing the energy up to 24 #x025; whereas the second one provides smaller speed ups while reduces energy up to 33 #x025;.
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