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The Tag Filter Cache: An Energy-Efficient Approach

Research Area: Processor Architecture Year: 2015
Type of Publication: Article
Authors:
Journal: 23rd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)
Abstract:
Power consumption in current high-performance chip multiprocessors (CMPs) has become a major design concern.The current trend of increasing the core count aggravates this problem. On-chip caches consume a significant fraction of the total power budget. Most of the proposed techniques to reduce the energy consumption of these memory structures are at the cost of performance, which may become unacceptable for high-performance CMPs. On-chip caches in multi-core systems are usually deployed with a high associativity degree in order to enhance performance. Even first-level caches are currently implemented with eight ways. The concurrent access to all the ways in the cache set is costly in terms of energy.
[Bibtex]

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