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Balancing Task Resource Requirements in Embedded Multithreaded Multicore Processors to Reduce Power Consumption
| Research Area: | Processor Architecture | Year: | 2010 |
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| Type of Publication: | In Proceedings | Keywords: | microprocessor chips;multi-threading;power consumption;scheduling; |
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| Book title: | Proceedings of the 18th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2010) | ||
| Pages: | 200 - 4 | ||
| Month: | February | ||
| ISBN: | 978-1-4244-5672-7 | ISSN: | 1066-6192 |
| Note: |
task resource requirements;embedded multithreaded multicore processors;power consumption reduction;power reduction techniques;dynamic voltage scaling;global DVS;
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| Abstract: |
Power consumption is a major design issue in modern microprocessors. Hence, power reduction techniques, like dynamic voltage scaling (DVS), are being widely implemented. Unfortunately, they impact on the task execution time so difficulting schedulability of hard real-time applications. To deal with this problem, this paper proposes a power-aware scheduler for coarse-grain embedded multicore processors implementing global DVS. To this end, this work presents two heuristics, namely Balanced Memory and Balanced CPU, which distribute the task set among cores focusing on resource utilization. Results show that with respect to a system not implementing DVS, two or five DVS levels achieve energy savings by about 35% or 51%, respectively.
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