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Exploiting wiring resources on interconnection network: Increasing path diversity

Research Area: Network-On-Chip Year: 2008
Type of Publication: In Proceedings Keywords: Electric network topology;Internet;Telecommunication;Wire;
Authors:
Book title: Parallel, Distributed and Network-Based Processing, 2008. PDP 2008. 16th Euromicro Conference on
Pages: 20 - 29
Address: Toulouse, France
Note:
Chip multi processor (CMP);Communication performances;Key parameters;Latency increase;Off chip;On Chip Network (OCN);Packet size (PS);Parallel links;Path diversity;Performance results;Space division multiplexing (SDM);
Abstract:
On-chip networks are the answer to the growing demands for high communication performance of chip multiprocessors. These networks have a number of characteristics that make their design quite different to off-chip networks. In particular, wires are an abundant available resource inside the chip. In this paper, we explore how to organize the huge wiring capabilities available in on-chip networks. In particular, we analyze the option of distributing the wires among several parallel links connecting the same two switches. This technique is known as Space Division Multiplexing (SDM). The number of parallel sub-links and their width are two key parameters that are studied together with the relationship with the mean packet size. The paper shows that SDM is a technique to take into account in on-chip networks since it allows to highly increase the network accepted traffic at the expense of a small latency increase or even no increase. Moreover, in some networks, it allows to reduce the network hardware, providing similar performance results, which results in a reduction in the consumption of area and power. © 2008 IEEE.
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