Home List of Publications



Year: 2010

  • Montaner, H., Silla, F., Fröning, H. & Duato, J (2010). Getting Rid of Coherency Overhead for Memory-Hungry Applications. In Cluster Computing (CLUSTER), 2010 IEEE International Conference on, pages 48 -57. [More] [Online version]
  • Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H (2010). Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. In Networking, Architecture and Storage (NAS), 2010 IEEE Fifth International Conference on, pages 218 -227. [More] [Online version]
  • Juan, C. M., Toffetti, G., Abad, F. & Cano Reyes, J (2010). Tangible Cubes Used as the User Interface in an Augmented Reality Game for Edutainment. In Advanced Learning Technologies (ICALT), 2010 IEEE 10th International Conference on, pages 599 -603. [More] [Online version]
  • Montaner, H., Silla, F. & Duato, J (2010). A practical way to extend shared memory support beyond a motherboard at low cost. In Proceedings of the 19th ACM International Symposium on High Performance Distributed Computing, pages 155-166. Chicago, Illinois : ACM. [More] [Online version]
  • Nachiondo, T., Flich, J. & Duato, J. (2010). Buffer Management Strategies to Reduce HoL Blocking. Parallel and Distributed Systems, IEEE Transactions on, 21(6), 739 - 753. [More] [Online version]
  • Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho Villanueva, J. et al (2010). Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. In Networks-on-Chip (NOCS), 2010 Fourth ACM/IEEE International Symposium on, pages 25 -32. [More] [Online version]
  • Hernández, C., Roca, A., Silla, F., Flich, J. & Duato, J (2010). Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. In 2010 ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pages 35 - 42. Grenoble, France : ACM. [More] [Online version]
  • Hernández, C., Silla, F. & Duato, J (2010). A Methodology for the Characterization of Process Variation in NoC Links. In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pages 685-690. Dresden, Germany : EDDA. [More] [Online version]
  • Rayo, D. B., Sahuquillo, J., Mohamed, H. H., Petit, S. & Duato, J (2010). Balancing Task Resource Requirements in Embedded Multithreaded Multicore Processors to Reduce Power Consumption. In Proceedings of the 18th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2010), pages 200 - 4. [More] [Online version]
  • Alonso, M., Coll, S., Martínez, J. M., Santonja, V., Lopez, P. & Duato, J. (2010). Power saving in regular interconnection networks. Parallel Computing, 36(12), 696 - 712. [More] [Online version]
  • Triviño, F., Sánchez, J. L., Alfaro, F. J. & Flich, J. (2010). Virtualizing network-on-chip resources in chip-multiprocessors. Microprocessors and Microsystems, In Press, Uncorrected Proof, -. [More] [Online version]
  • Duato, J., Peña, A. J., Silla, F., Mayo, R. & Quintana-Ort, E. S (2010). rCUDA: Reducing the number of GPU-based accelerators in high performance clusters. In High Performance Computing and Simulation (HPCS), 2010 International Conference on, pages 224 - 231. Caen, France. [More] [Online version]
  • Morillo, P., Rueda, S., Orduna, J. M. & Duato, J (2010). Ensuring the performance and scalability of peer-to-peer distributed virtual environments. In Future Generation Computer Systems, pages 905 - 915. P.O. Box 211, Amsterdam, 1000 AE, Netherlands. [More] [Online version]
  • Duato, J., Igual, F. D., Mayo, R., Peña, A. J., Quintana-Orti, E. S. & Silla, F (2010). An efficient implementation of GPU virtualization in high performance clusters. In Euro-Par 2009 – Parallel Processing Workshops, pages 385 - 394. Delft, Netherlands. [More] [Online version]
  • Ferrer, J.-L., Baydal, E., Robles, A., Lopez, P. & Duato, J (2010). A Scalable and Early Congestion Management Mechanism for MINs. In Proceedings of the 18th Euromicro Conference on Parallel, Distributed and Network-Based Processing, PDP 2010, pages 43 - 50. Piscataway, NJ, USA. [More] [Online version]
  • Fernandez-Pascual, R., Garcia, J. M., Acacio, M. E. & Duato, J. (2010). Dealing with transient faults in the interconnection network of CMPs at the cache coherence level. IEEE Transactions on Parallel and Distributed Systems, 21(8), 1117 - 1131. [More] [Online version]

Year: 2009

  • Ros, A., Cintra, M., Acacio, M. E. & Garcia, J. M (2009). Distance-aware round-robin mapping for large NUCA caches. In High Performance Computing (HiPC), 2009 International Conference on, pages 79 -88. [More] [Online version]
  • Petit, S., Ubal, R., Sahuquillo, J. & Lopez, P (2009). A power-aware hybrid RAM-CAM renaming mechanism for fast recovery. In Computer Design, 2009. ICCD 2009. IEEE International Conference on, pages 150 -157. [More] [Online version]
  • Rodrigo, S., Hernández, C., Flich, J., Silla, F., Duato, J., Medardoni, S. et al (2009). Yield-oriented evaluation methodology of network-on-chip routing implementations. In System-on-Chip, 2009. SOC 2009. International Symposium on, pages 100 -105. [More] [Online version]
  • Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H (2009). Balanced Dimension-Order Routing for k-ary n-cubes. In Parallel Processing Workshops, 2009. ICPPW '09. International Conference on, pages 499 -506. [More] [Online version]
  • Rodrigo, S., Medardoni, S., Flich, J., Bertozzi, D. & Duato, J. (2009). Efficient implementation of distributed routing algorithms for NoCs. Computers Digital Techniques, IET, 3(5), 460 -475. [More]
  • Petit, S., Ubal, R., Sahuquillo, J., Lopez, P. & Duato, J (2009). An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions. In Nunez, A. & Carballo, P. P. (editors), Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on, pages 635 -642. [More] [Online version]
  • Chirivella, V., Alcover, R., Flich, J. & Duato, J (2009). Dependability analysis of a fault-tolerant network reconfiguring strategy. In Sips, H., Epema, D. & Lin, H.-X. (editors), Euro-Par 2009 Parallel Processing, pages 1040 - 1051. Delft, Netherlands : Springer. [More] [Online version]
  • Holsmark, R., Kumar, S., Palesi, M. & Mejia, A (2009). HiRA: A methodology for deadlock free routing in hierarchical networks on chip. In Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on, pages 2 -11. [More] [Online version]
  • Mejia, A., Palesi, M., Flich, J., Kumar, S., Lopez, P., Holsmark, R. et al. (2009). Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 17(3), 356 -369. [More] [Online version]
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