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Year: 2011

Year: 2010

  • Ros, A., Acacio, M. E. & Garcia, J. M. (2010). A Direct Coherence Protocol for Many-Core Chip Multiprocessors. Parallel and Distributed Systems, IEEE Transactions on, 21(12), 1779 -1792. [More] [Online version]
  • Escudero-Sahuquillo, J., Garcia, P. J., Quiles, F. J., Flich, J. & Duato, J (2010). Cost-Effective Congestion Management for Interconnection Networks Using Distributed Deterministic Routing. In 16th International Conference on Parallel and Distributed Systems (ICPADS 2010). Shanghai, China. [More]
  • Roca, A., Flich, J., Silla, F. & Duato, J (2010). VCTlite: Towards an Efficient Implementation of Virtual Cut-Through Switching in On-Chip Networks. In 17th Int'l Conference on High Performance Computing (HiPC). Goa,India. [More]
  • Ros, A., Cuesta Sáez, B., Fernández-Pascual, R., Gomez, M. E., Acacio, M. E., Robles, A. et al (2010). EMC^2: Extending Magny-Cours Coherence for Large-Scale Servers. In 17th Int'l Conference on High Performance Computing (HiPC). Goa, India. [More]
  • Gilabert, F., Silla, F., Gomez, M. E., Lodde, M., Roca, A., Flich, J. et al. (2010). Designing Network On-Chip Architectures in the Nanoscale Era. CRC Press. [More] [Online version]
  • Strano, A., Hernández, C., Silla, F. & Bertozzi, D (2010). Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip. In System on Chip (SoC), 2010 International Symposium on, pages 43 -48. [More] [Online version]
  • Serrano, M., Sahuquillo, J., Mohamed, H. H., Petit, S. & Duato, J (2010). A Scheduling Heuristic to Handle Local and Remote Memory in Cluster Computers. In High Performance Computing and Communications (HPCC), 2010 12th IEEE International Conference on, pages 35 -42. [More] [Online version]
  • Roca, A., Flich, J., Silla, F. & Duato, J (2010). A Latency-Efficient Router Architecture for CMP Systems. In Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference on, pages 165 -172. [More] [Online version]
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