Staff Members
Network-On-Chip
Description
Network-on-Chip (NoC) is an emerging paradigm for communications within large systems implemented on a single silicon chip. Sgroi et al. call "the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology. "In a NoC system, modules such as processor cores memories and specialized IP blocks exchange data using a network as a public transportation" sub-system for the information traffic. An NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches. An NoC is similar to a modern telecommunications network, using digital bit-packet switching over multiplexed links. Although packet-switching is sometimes claimed as necessity for a NoC, there are several NoC proposals utilizing circuit-switching techniques. This definition based on routers is usually interpreted so that a single shared bus, a single crossbar switch or a point-to-point network are not NoCs but practically all other topologies are. This is somewhat confusing since all above mentioned are networks (they enable communication between two or more devices) but they are not considered as network-on-chips. Note that some articles erroneously use NoC as a synonym for mesh topology although NoC paradigm does not dictate the topology. Likewise, the regularity of topology is sometimes considered as a requirement which is, obviously, not the case in research concentrating on "application-specific NoC topology synthesis".
Members
Publications
- Duato, J., Peña, A. J., Silla, F., Mayo, R. & Quintana-Orti, E. S (2011). Performance of CUDA Virtualized Remote GPUs in High Performance Clusters. In Parallel Processing (ICPP), 2011 International Conference on, pages 365 -374. [More]
- Roca, A., Hernández, C., Flich, J., Silla, F. & Duato, J (2011). A Distributed Switch Architecture for On-Chip Networks. In Parallel Processing (ICPP), 2011 International Conference on, pages 21 -30. [More]
- Hernández, C., Silla, F. & Duato, J (2011). Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations. In Parallel Processing (ICPP), 2011 International Conference on, pages 41 -50. [More]
- Escudero-Sahuquillo, J., Gran, E. G., Garcia, P. J., Flich, J., Skeie, T., Lysne, O. et al (2011). Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks. In Parallel Processing (ICPP), 2011 International Conference on, pages 662 -672. [More]
- Camacho Villanueva, J., Flich, J., Roca, A. & Duato, J (2011). PC-Mesh: A Dynamic Parallel Concentrated Mesh. In Parallel Processing (ICPP), 2011 International Conference on, pages 642 -651. [More]
Projects
- Nanoscale Silicon-Aware Network-on-Chip Design Platform
- Comunication-centric heterogeneous Multi-Core ArchitectureS