Staff Members
Network-On-Chip
Description
Network-on-Chip (NoC) is an emerging paradigm for communications within large systems implemented on a single silicon chip. Sgroi et al. call "the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology. "In a NoC system, modules such as processor cores memories and specialized IP blocks exchange data using a network as a public transportation" sub-system for the information traffic. An NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches. An NoC is similar to a modern telecommunications network, using digital bit-packet switching over multiplexed links. Although packet-switching is sometimes claimed as necessity for a NoC, there are several NoC proposals utilizing circuit-switching techniques. This definition based on routers is usually interpreted so that a single shared bus, a single crossbar switch or a point-to-point network are not NoCs but practically all other topologies are. This is somewhat confusing since all above mentioned are networks (they enable communication between two or more devices) but they are not considered as network-on-chips. Note that some articles erroneously use NoC as a synonym for mesh topology although NoC paradigm does not dictate the topology. Likewise, the regularity of topology is sometimes considered as a requirement which is, obviously, not the case in research concentrating on "application-specific NoC topology synthesis".
Members
- Flich, Jose
- Martínez, Jose Maria
- Hernández, Carles
- Tornero, Rafael
- Picornell, Tomas
- Scotti, Vincenzo
Publications
- Picornell, T., Hernández, C., Flich, J. & Duato, J. (2020). Enforcing Predictability of Many-cores with DCFNoC. IEEE Transactions on Computers. [More]
- Gorgues, M. & Flich, J. (2019). A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems. 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). [More]
- Picornell, T., Hernández, C., Duato, J. & Flich, J. (2019). DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip. 56th Annual Design Automation Conference 2019. [More]
- Flich, J. (2018). Exploring Manycore Architectures for Next-Generation HPC Systems through the MANGO Approac. Microprocessors and Microsystems. [More]
- Duro, J., Petit, S., Sahuquillo, J. & Gomez, M. E. (2017). Modeling a Photonic Network for Exascale Computing. 2017 International Conference on High Performance Computing & Simulation (HPCS). [More]
Theses
- Addressing Manufacturing Challenges in NoC-based ULSI Designs
- Improving Network-on-Chip Performance in Multi-Core Systems
- Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip
- Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors
- High Performance and Power Efficient On-Chip Network Designs through Multiple Injection Ports
