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Improving Energy and Area Scalability of the Cache Hierarchy in CMPs

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Research Area: Computer Architecture
Status: Finished Degree: Bachelor
Directors: Students:
Proposed start date: 2013-02-01 Proposed end date: 2017-02-01
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Description:

As the core counts increase in each chip multiprocessor generation, CMPs should improve scalability in performance, area, and energy consumption to meet the demands oflarger core counts. Directory-based protocols constitute the most scalable alternative. A conventional directory, however, suffers from an inefficient use of storage and energy. First, the large, non-scalable, sharer vectors consume unnecessary area and leakage, especially considering that most of the blocks tracked in a directory are cached by a singlecore. Second, although increasing directory size and associativity could boost system performance by reducing the coverage misses, it would come at the expense of area andenergy consumption.This thesis focuses and exploits the important differences of behavior between private and shared blocks from the directory point of view. These differences claim for a separate management of both types of blocks at the directory. First, we propose the PS-Directory,a two-level directory cache that keeps the reduced number of frequently accessed shared entries in a small and fast first-level cache, namelySharedDirectory Cache, and uses a larger and slower second-level Private Directory Cache to track the large amount of private blocks. Entries in the Private Directory Cache do not implement the sharervector, which allows important silicon area savings. Speed and area reasons suggest the use of eDRAM technology, much denser but slower than SRAM technology, for the Private Directory Cache, which in turn brings further energy savings. Experimental results show that, compared to a conventional directory, the PS-Directory improves performance while also reducing silicon area and energy consumption.

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