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Adaptive Prefetching and Cache Partitioning for Multicore Processors

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Research Area: Computer Architecture
Status: Finished Degree: Bachelor
Directors: Students:
Proposed start date: 2014-09-01 Proposed end date: 2018-09-01
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Description:

This thesis focuses on reducing the inter-application interference, both in the shared cache and in the access to the main memory. To reduce the inter-application interference in the access to main memory, the proposed approach regulates the aggressiveness of each core prefetcher, and selectively activates or deactivates some of them, depending on their individual performance and the main memory bandwidth requirements of the other cores. With respect to interference in shared caches, this thesis proposes two LLC partitioning techniques that give more cache space to the applications that have their progress diminished due inter-application interferences. The first cache partitioning proposal requires dedicated hardware not available in commercial processors,so it has been evaluated using a simulation framework. The second proposal dealing with cache partitioning presents a family of partitioning policies that overcome the limitations in the number of partitions and the number of avail-able ways by grouping applications and overlapping cache partitions, so multiple applications share the same ways. Since it has been implemented using the cache partitioning features of modern Intel processors it has been evaluated in a real machine.

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