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Design Space Exploration for Networks On-chip

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Research Area: Network-On-Chip
Status: Finished Degree: Bachelor
Directors: Students:
Proposed start date: 2007-09-01 Proposed end date: 2011-09-01
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Description:

This dissertation focuses on the development of a new set of front-end design, modeling and simulation tools for layout-aware pruning of the design space toward the most promising candidates. As an outcome of this disser-tation, NoC designers will be able to take advantage of a new set of design space exploration tools reducing time-to-market and bridging the accuracy gap with the lower layers of the design process.

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