High-performance architectures for high-radix switches.
|Research Area:||Swicth Architectures|
|Proposed start date:||2005-01-10||Proposed end date:||2008-12-16|
To benefit from a reduction in the latency and reduce both consumption and cost, the optimal number of ports on a switch has been increasing over time. However, traditional architectures have lagged well for poor performance or due to problems of scalability with the number of ports. In this thesis proposes a new switch architecture valid for high level switches called Partitioned Crossbar Input Queued (PCIQ). This architecture solves the problem of excessive memory requirements in the design of high level architectures. In addition PCIQ defines a new family of switch architectures. PCIQ is based on a crossbar intelligent partitioning, dividing it into sub-crossbars, requiring less memory resources than the other proposals for high-grade switches and achieves greater efficiency due in part to an increase in the efficiency of employees referees design. In this sense, PCIQ uses two rotating priority arbiters (one for each sub-crossbar) which have a cost linear and logarithmic response over time as the number of switch ports. In addition PCIQ has a cost (measured in terms of memory requirements, complexity of the crossbar and complexity in the arbitration) similar or even lower than basic as CIOQ organizations. However PCIQ can achieve maximum efficiency for uniform traffic distributions. The packet blocking at the beginning of line (HOL or English) dramatically reduces the switch performance. Traditional solutions to eliminate HOL blocking are not scalable with the number of ports or require complex architectures. In this thesis proposes a technique for congestion control that eliminates the HOL blocking call RECN-IQ. RECN-IQ is designed to switch with memories only to entry and is a highly efficient technique