The Workshop

INA-OCMC is a network oriented workshop presenting original work in the field of on-chip, multi-chip interconnection network architecture. The workshop aims at bringing together researchers and engineers from industry and academia to share ideas and thoughts about networking of devices in both the off-chip and the on-chip environment, each with its own design constraints. This is the eighth edition of the workshop. In the previous editions the workshop exhibited a competent audience and interesting discussions arose from the different presentations of authors and from the keynote, thus promoting joint research initiatives.

Organizing Committee

General Chairs

Program Chairs

Steering Committee


Technical Scope

Scalable interconnect architectures form the solid base on top of which future complex computing platforms will be developed. The interconnect architecture should be as high performance as its connecting nodes, thus enabling the expected exponential growth in system concurrency. The number of nodes either on-chip or off-chip that need to communicate in modern embedded and HPC systems is constantly increasing. This trend poses significant challenges to the interconnection network designers that tackle a multidimensional problem involving hardware and software components such as network interfaces, switches, and communication library APIs.

At the same time, new usage models of mobile devices together with the digital convergence trend require that largely different operating conditions are accommodated by a single, deeply reconfigurable design. In this direction, heterogeneity could take the form of runtime specialization rather than design time customization. Similarly, manufacturing yield and device availability could be significantly improved by the device capability to adapt to hardly predictable and even changing operating conditions at runtime.

The INA-OCMC workshop focuses on the presentation of novel interconnect architectures arising in several domains, such as embedded MPSoCs, CMPs, Cloud/Datacenter, microservers and HPC systems, designed for increased performance and energy/cost efficiency under demanding physical, architectural and technological constraints which translate to contradictory objectives and most commonly to very tight energy budgets. We invite contributions of previously unpublished results on all aspects of interconnection network architectures that include but are not limited to:

  • Multi-Chip Interconnection Networks, including Cluster Interconnects

  • Networks-on-Chip (NoC)

  • Switch, buffering, and routing architectures

  • Flow control and congestion management in switching fabrics

  • Architectures for QoS support

  • Virtualization

  • Topology exploration

  • Reconfigurable/Programmable interconnect components

  • Reliability, availability, fault tolerance

  • Programming models for communication-centric systems


Special Journal Issue

Following the example of the 2012 and 2013 workshops, the best papers of the INA-OCMC 2014 will be published in a special issue of a selected journal. The selection of the best papers will be based on paper reviews and the quality of the oral presentation at the workshop..


Paper submission - Camera-ready

Submitted papers will be handled by an international Program Committee accepting only high-quality submissions. The submission and the review process will be handled electronically via EasyChair link. Papers must be in PDF format and should include title, authors and affiliations as well as the e-mail address of the contact author. Papers must be formatted in accordance to the ACM two-column style. ACM Word and LaTeX style templates are available at this link. Submissions must be limited to 4 pages. Papers deviating significantly from the paper size and formatting rules may be rejected without review.


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Important Dates

  • Submission deadline: November 8st, 2013.

  • Author Notification: December 11th, 2013.

  • INA-OCMC workshop: January 22nd, 2014.


Technical Program Committee

  • Federico Angiolini, iNoCS, Switzerland

  • Nikos Chrysos, IBM Research Zurich, Switzerland

  • Marcello Coppola, ST, France

  • Natalie Enright Jerger, University of Toronto, Canada

  • Pedro Javier Garcia, UCLM, Spain

  • Francisco Gilabert, Intel, Germany

  • Emmanouil Kalligeros, University of the Aegean, Greece

  • Janusz Kleban, Poznan University of Technology, Poland

  • Partha Kundu, Juniper Networks, USA

  • Hiroki Matsutani, Keio University, Japan

  • Jose Angel Gregorio Monasterio, Univ. of Cantabria, Spain

  • Chrysostomos Nicopoulos, University of Cyprus, Cyprus

  • Steven Nowick, Columbia University, USA

  • Maurizio Palesi, Kore University, Italy

  • Vassos Soteriou, Cyprus University of Technology, Cyprus

  • Eitan Zahavi, Mellanox, Israel

  • Holger Fronning, University of Heidelberg, Germany

  • Gerard Rauwerda, Recore Systems, Netherlands

  • John Bainbridge, Qualcomm, USA


Workshop Program

Click here to view the technical program of the workshop.


Contact us

For any information/problem/suggestion, feel free to contact:



Associated with

Published by ACM



ACM approval has been received! INA-OCMC papers will be published in ACM Digital library.


Submission Deadline has been extended to November 8th.